Semiconductor devices are fabricated step-by-step, beginning with a silicon wafer (substrate), implanting various ions, creating various circuit structures and elements, and depositing various insulating and conductive layers. Some of these layers are subsequently patterned by photoresist and etching, or similar processes, which results in topological features on the surface of the substrate. Subsequent layers over the topological layers inherit, and sometimes exacerbate, the uneven topology of the underlying layers. Such uneven (irregular, non-planar) surface topology can cause undesirable effects and/or difficulties in the application of subsequent layers and fabrication processes.
Hence, it is known, at various stages of semiconductor fabrication, to planarize a layer. Various techniques for planarizing a layer by etching or chemical-mechanical ("chem-mech") polishing are known. For example, chem-mech polishing of a semiconductor substrate is disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155 and 4,944,836, incorporated by reference herein.
The present invention is directed to chem-mech polishing processes, which generally involve "rubbing" a wafer with a polishing pad in a slurry containing both an abrasive and chemicals. Typical slurry chemistry is KOH (Potassium Hydroxide), having a pH of about 11. A typical silica-based slurry is "SC-1" available from Cabot Industries. Another slurry based on silica and cerium (oxide) is Rodel "WS-2000".
It is also known to use mechanical or chem-mech polishing techniques to completely remove (rather than to partially remove, or planarize) a layer that has been deposited. For example, U.S. Pat. No. 5,142,828, incorporated by reference herein, describes a process whereby a defective metallization layer is removed from the top of an electronic component such as an integrated circuit or a copper/polyimide substrate by polishing with a rotating pad and a slurry. Non-defective underlying metallization layers are preserved, and a new metallization layer is fabricated to replace the defective layer. For example, mechanical polishing of a copper layer, in a customizable high density copper/polyimide substrate, using a slurry of alumina grit with alumina particles between 0.05-3.0 microns suspended in solution, is disclosed in this patent. Slurries using silicon carbide and diamond paste are also described in the patent. The polishing of a tungsten layer is also suggested in the patent.
The aforementioned U.S. Pat. No. 4,910,155 discloses wafer flood polishing, and discusses polishing using 0.06 micron alumina particles in deionized water. The use of silica particulates is also discussed. Particulates of sizes as small as 0.006 microns (average size), and as large as 0.02 microns are discussed in this patent. The use of SiO.sub.2 particulates (average diameter of 0.02 microns) suspended in water is also discussed in this patent.
Generally, chem-mech polishing is known for planarizing dielectric films. Generally, the penultimate layers of an integrated circuit are alternating dielectric and conductive layers forming interconnects, and the ultimate layer is a passivation layer, such as phosphosilicate glass (PSG). It is generally inconvenient and impractical to check the device at each step in the process since 1) functionally, the various gates and structures may not be interconnected at a particular stage, and 2) it is generally undesirable to remove the wafer from the "clean" fabrication environment at intermediate steps.
U.S. Pat. No. 4,956,313 discloses a via-filling and planarization technique. This patent discusses a planarization etch to remove portions of a metal layer lying outside of vias, while simultaneously planarizing a passivation layer, to provide a planarized surface upon which subsequent metal and insulator layers can be deposited. The use of an abrasive slurry consisting of Al.sub.2 O.sub.3 particulates, de-ionized water, a base, and an oxidizing agent (e.g., hydrogen peroxide) is discussed, for etching tungsten and BPSG.
In the process of manufacturing semiconductor devices from silicon wafers, there is always the possibility that the device (or entire wafer) will be mis-manufactured. For example, a top metal layer (M.sub.n) may exhibit voids reducing the cross-sectional area of conductive lines. Various other problems such as corrosion, mechanical stress and incomplete etching may be encountered. In the main hereinafter, voids in metal lines are discussed as an exemplary fault needing repair. Reference is made to "Stress Related Failures Causing Open Metallization, by Groothuis and Schroen, IEEE/IRPS, 1987, CH2388-7/87/0000-0001, pp.1-7, incorporated by reference herein.
Once a fault is identified, it can sometimes be repaired, and techniques such as focussed ion beam "micro-surgery" are known. However, in order to advantageously employ these repair techniques, or to remanufacture a defective layer it is necessary to strip off one or more of the top layers (e.g., passivation, metal, dielectric) of the device. These stripping techniques have as their goal returning the device (or a plurality of devices, when an entire wafer is processed in this manner) to a pre-existent, incomplete stage of manufacture, from which point onward, the device can be repaired or remanufactured.
Wet etching is one known technique for removing (stripping) layers of material in semiconductor devices. However, wet etching cannot be made to etch in any way except isotropically, which means that structures will be distorted in the horizontal (lateral) extent. Further, wet etching of oxide can destroy metal lines and bond pads.
Plasma etching, on the other hand, can be either isotropic or anisotropic, but it is usually unable to continue etching through all of the layers of material (e.g., oxide removal in the presence of metal lines) in the same cycle. This limitation forces the use of a series of different plasma etch processes, and simply does not work satisfactorily. In many instances, insulating layers underlying metal areas are also etched away, with the result that the metal lines will lift off.
U.S. Pat. No. 4,980,019, entitled ETCH-BACK PROCESS FOR FAILURE ANALYSIS OF INTEGRATED CIRCUITS, (Baerg et al.; Dec. 25, 1990) discloses a method for etching exposed dielectric layer portions of an integrated circuit device to expose an underlying metal layer, by reactive ion etching (RIE) of the passivation layer. The technique is directed to etching back a delidded integrated circuit device.
U.S. Pat. No. 4,609,809, incorporated by reference herein, discloses method and apparatus for correcting delicate wiring of IC device employing an ion beam.
These techniques are unsatisfactory in that they alter the topography of the devices while film (layer) removal is taking place. In other words, they do not return the device to a truly pre-existent stage of fabrication. Consequently, significant losses in device throughput are incurred.